Paul Tingey

"Making Multicore Work" Seminars

February has been a particularly busy month. So busy, in fact, that I was not able to make time to be at the Mobile World Congress in Barcelona. Instead I have spent most of the month completing a tour of seven European cities presenting at a joint Wind River/Freescale/Virtutech seminar series.

The theme of the seminar was "Making Multicore Work". The presentations included details of Freescale's newest and upcoming multicore devices, Virtutech's virtualised software development technology and Wind River's latest VxWorks SMP and multicore debug tools releases.

The subject of the seminar seemed particularly popular with the number and variety of attendees at each venue exceeding our expectations. Attendees included engineers and development managers from the Mobile Handset, Automotive, Defense and Networking industries.

The focus for my particular presentation was Symmetric Multi-Processing (more specifically VxWorks SMP) during which I outlined the challenges involved in programming for a multicore environment. I also presented a live demonstration of VxWorks SMP (running on the new MPC8572E based Freescale reference platform) in which I attempted to highlight those programming practices which may lead to problems in a multicore environment.

During my presentation I was keen to outline that problems may not only be caused by "bad" programming practices but may also be the result of apparently acceptable program structure which may fail due to assumptions made by the programmer. For example, programmers often expect memory operations to be performed in the order in which they appear in source code. However, modern processors use out-of-order execution [Wikipedia reference] techniques which may cause load/store operations to be re-ordered. In a single core system this is rarely (if ever) a problem due to the fact that the memory operation "pipeline" will be emptied/cleaned before or during the next context switch so the software knows little or nothing about the hardware optimisations happening beneath it. However, in a multicore system, where two or more tasks or ISRs are running concurrently, the programmer needs to be aware of the effect that out-of-order load/store operations may have and use appropriate memory barrier [Wikipedia reference] instructions where necessary. Without these memory barriers, out-of-order load/store operations on a multicore system could give rise to the worst kind of timing related bugs and race conditions.

I'm hoping that the audience at each of our venues took away something positive from the event. For myself, the event has reinforced my view that multicore devices will become increasingly commonplace over the next months and years. The attendance numbers and the reactions of attendees make it clear that engineers are being forced to think in terms of multicore (either Symmetric or Asymmetric multi-processing). The challenge for those engineers is to adapt the way they write code for a multicore environment whilst at the same time, fully utilising the hardware resources they have available.

Telecoms equipment can be cool (honestly)

Many years ago, at a previous company, I spent my days writing assembler code for the 68302 processor and watched enviously as other (more fortunate) engineers wrote "modern" C++ applications for Pentium-II desktop PCs. In the canteen at lunchtime, no-one wanted to listen to my witty anecdotes about humorous 68K register names. At a technology level, embedded systems just weren't "cool".

However, times are changing. Desktop PCs may now offer dual core processors but, in reality, todays technology revolution is driven by a telecoms infrastructure that enables rich applications based on VoIP, Multimedia services and mobile communications. On the back of this revolution, the technology inside telecoms infrastructure equipment is getting pretty cool.

Wind River today announced Carrier Grade Linux support for the Sun Microsystems UltraSPARC T1 processor, a device which can include up to eight cores (that's at least four times as many cores as are in a desktop machine) and offers a glimpse into the future of network equipment.

So what's so cool about this device? Well, until recently each blade in a chassis based telecoms system had a distinct purpose; there were blades for the application plane, blades for the control plane and blades for the data plane. However, Sun's latest CP3060 ATCA blade, running an UltraSPARC T1 multi-core processor, is capable of performing all of these multiple roles simultaneously.

The UltraSPARC T1 processor, which includes up to eight individual cores each of which runs four threads, does this by offering it's resources as (up to) 32 virtual processors. So an ATCA chassis populated with a number of Sun CP3060 blades could offer hundreds of virtual processors each of which can be allocated to either application plane, control plane or data plane processing. This offers the possibility of consolidating several blades into a single slot and therefore reducing the size of the overall system.

The performance of the UltraSPARC T1 [Wikipedia reference] is impressive too. The device uses hardware multi-threading to minimize idle time in each core which in turn increases performance per watt. That means that the UltraSPARC T1 processor only requires about 35% of the power budget of an ATCA slot meaning that it runs cooler and it leaves more of the power budget available for other features such as increased memory. What you end with is increased processing power for the same power budget.

Crucially, this improved power efficiency leads to a reduced power/cooling requirement for the same processing power. In fact, for this reason the UltraSPARC T1 has already won an award for being the Worlds First Eco-Responsible Processor. Any technology which attempts to bridge the gap between our hunger for technology and our need to cut energy consumption is to be welcomed.

The kind of flexibility offered by the UltraSPARC T1 processor will be crucial as the IP Multimedia Subsystem or IMS (a topic which I'll cover over the coming weeks) begins to roll out. As well as the core benefits offered by ATCA and a CGL compliant operating system (high-availability, manageability, etc), IMS also demands exactly the kind of high performance and scalability which the UltraSPARC T1 processor offers.

Despite what you may think, telecoms infrastructure equipment can be quite cool...